This application claims priority from Korean Patent Application No. 2001-13931, filed on Mar. 17, 2001, the contents of which are incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for fabricating the same and, more particularly, to a flash memory device having a charge-storage dielectric layer and a method for manufacturing the same.
2. Description of the Related Art
A flash memory device including a charge-storage dielectric layer, such as SONOS (Silicon-Oxide-Nitride-Oxide-Semiconductor) memory device, is typically composed of a polysilicon gate electrode, source and drain electrodes at both sides of the polysilicon gate electrode, and an ONO (Oxide-Nitride-Oxide) triple dielectric layer interposed between a semiconductor substrate and the polysilicon gate electrode as a charge-storage layer.
A conventional SONOS device structure is schematically shown in FIGS. 1, 2A, and 2B. FIG. 1 is a perspective view of the conventional SONOS device, FIG. 2A a cross-sectional view taken along the line 1A-1Axe2x80x2 in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line 1B-1Bxe2x80x2 in FIG. 1. Referring to FIGS. 1 to 2B, the conventional SONOS device includes an ONO layer 112 including a lower oxide layer 106xe2x80x94a nitride layer 108xe2x80x94an upper oxide layer 110 over a silicon semiconductor substrate 100, and a polysilicon gate line 114 formed on the ONO layer 112. However, the ONO layer 112 is formed not only on active regions 104 intersecting the gate line 114, but also on isolation regions 102 electrically isolating the active regions 104. That is, the ONO layer is formed on the entire regions (active region and isolation region) under the gate line 114.
For the SONOS flash memory device, there are several main modes of operation, for example, Programming, Erasing, and Reading. In the programming mode, a program voltage Vpp is applied to the gate line 114. If a source region 116a formed on an active region at one side of the gate line 114, and a drain region 116b formed on an active region at the other side of the gate line 114 are grounded to a semiconductor substrate 100, some of the electrons from the semiconductor substrate 100 tunnel through the lower oxide layer 106 by a F-N (Fowler-Nordheim) tunneling mechanism and are injected into the nitride layer 108. Accordingly, a threshold voltage of the transistor becomes high enough to program data.
For the erasing mode, the gate line 114, the drain region 116b, and the source region 116a are opened, and the program voltage Vpp is applied to the substrate 100. Then, the electrons injected (trapped) within the nitride layer 108 are forced into the substrate 100. Accordingly, the threshold voltage becomes low, thereby erasing the data.
Further, in the reading mode, a reading voltage Vr is applied to the gate line 114, and a current between the source 116a and the drain 116b is detected. By using a sensing circuit measuring the current during an application of the reading voltage Vr, it is possible for a reading operation to be performed on a specific memory cell.
However, as semiconductor devices become more highly integrated, a topological size of an active region and an isolation region inevitably becomes narrower, decreasing a spacing between adjacent cells. As described above, because the SONOS flash memory device traps electrons within the ONO layer 112, especially, the nitride layer 108, or by releasing the trapped electrons, data loss can easily occur in the conventional SONOS flash memory device because the ONO layer is formed not only on the active regions 104, but also on the isolation regions 102. With the conventional SONOS device, adjacent cells are thus interconnected thorough the ONO layer. Furthermore, if the spacing between the adjacent cells becomes narrower, the electrons trapped in the ONO layer formed on the narrow isolation region may undesirably influence the flash memory operations.
The present invention provides a flash memory device preventing disturbances caused by adjacent cells during a memory cell operation.
According to an embodiment the present invention, adjacent isolation regions formed on a semiconductor substrate. The adjacent isolation regions define an active region therebetween. A charge-storage dielectric layer is formed only on the active region. A gate line overlies the charge-storage layer and intersects the isolation regions and the active region.
According to another embodiment of the present invention, a method for forming the flash memory device includes forming a charge-storage dielectric layer on a semiconductor substrate. The charge-storage dielectric layer is patterned to expose regions of the semiconductor substrate. Isolation regions are formed in the exposed regions of the semiconductor substrate. The isolation regions define active regions therebetween. The patterned charge-storage dielectric layer is self-aligned with the isolation regions. A conductive layer overlies the patterned charge-storage dielectric layer. The conductive layer and the patterned charge-storage layer are patterned to form gate lines overlying the patterned charge-storage layer and extending across the active regions. Preferably, the charge-storage layer is formed only on the active region and includes a lower oxide layer, a nitride layer, and an upper oxide layer (ONO layer) sequentially staked on the semiconductor substrate.